Course Name:
System Development and
Programming with the Analog Devices Blackfin processor family
Course Objectives:
The main course objective is to instill to the attendee a high level of confidence to create an efficient Blackfin® Processor based system. By being exposed to the various capabilities and features of the Blackfin processor and VDSP tool chain, the attendee will be better armed to tackle any issues that arise in their specific system implementations.
Course Description:
This is a practical and interactive course that is designed to systematically teach how to use the Blackfin processor to its fullest potential. Emphasis is placed on understanding the steps required to create an efficient Blackfin CPU based system in the way that ADI had intended the processor to be used. Several hands on exercises provide an opportunity for the instructor to work one on one with the attendee. Throughout the workshop, attendees are encouraged to ask questions.
The VisualDSP++ IDDE is covered in detail, including topics on projects and project configuration, the build process, and debug features. Tools based optimizations including compiler and linker optimization are covered. The salient features of System Services and Device Drivers are first introduced. Later sections on specific peripherals or system features will connect back to the related Services or Driver API. An understanding of the Blackfin architecture will enable getting the best performance out of the processor. Architecture topics covered include loop/branch optimization and interrupt handling, L1 Memory configuration (ie L1 SRAM and Cache), specialized instructions including the quad 8-bit Video ALU operations, and DMA operation between peripherals and memory, as well as from memory to memory. The usage and capabilities of the various I/O and timer peripherals are discussed in detail. A section on booting covers what happens during the boot process, creating boot image files, and discussing how to get them into the target system. Hardware considerations such as operation of the power management and reset are also discussed. Hardware development tools, such as evaluation boards and ICE's are also covered, including setting up hardware debug sessions and other hardware debug topics. An introduction into VDK (Visual DSP Kernel) is also covered in the workshop.
Throughout the course, a number of hands on exercises will take the attendee through the various aspects of the software development process. Topics covered through exercises include setting up and building projects, C language programming (eg using intrinsics, exploring different data types), various optimizations (eg compiler, linker, mixed C/assembly), code debugging (eg profiling, plotting, pipeline analysis), simulation (eg DMA, interrupts, stream I/O), and 'C' programming support (eg System Services and Device Drivers). One set of exercises will focus on bringing the various elements together (eg peripheral setup, DMA, interrupts, etc) in the setup of a typical application framework, initially in straight C and later using the System Services and Device Drives programming model.
A detailed course outline can be found at WS_BFDEV-OUT.pdf.
Who Should Attend:
Code Developers needing to know how to
get the highest performance from their algorithms, System Designers needing
to make informed decisions on design tradeoffs, and Hardware Designers
needing to develop external peripheral interfaces
Prerequisite:
It is highly recommended to watch the Visual Learning and Development (VLD) Video Tutorial entitled "Blackfin® Core Architecture". Previous embedded microprocessor experience would be an asset (hardware and/or software).
Duration:
3.5 days
Course Fee:
Register early and save up to 6% on the workshop fee:
$1500 USD (North America) / €1500 EUR (Europe) - If paid by company check, wire/ACH, or money order, on or before the Run/Cancel Decision Date
$1547 USD (North America) / €1547 EUR (Europe) - If paid by credit card or PayPal, on or before the Run/Cancel Decision Date
$1595 USD (North America) / €1595 EUR (Europe) - If paid after the Run/Cancel Decision Date
Schedule:
DATES |
RUN/CANCEL DECISION DATE |
PLACE |
STATUS |
TBD |
|
Munich, Germany |
Coming soon! |
TBD |
|
Norwood, MA |
Coming Soon! |
TBD |
|
Anywhere Worldwide |
Contact Us |
This workshop can also be provided at your facilities.
Please send your request to info@kaztek.com.
Workshop participants can get 50% off the regular price on their choice of any 3 Analog Devices hardware or software development tools.
Click here to ask for more details.
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