Course Name:

System Development with CrossCore Embedded Studio (CCES) with the 5th Generation multicore SHARC Processors

Course Objectives:

The main course objective is to understand the SHARC architecture (with a focus on the ADSP-SC5xx/215xx Sharc Processor Family members) sufficiently to enable DSP system designers to resolve hardware/software issues with their applications. Additional goals include gaining a thorough understanding of SHARC code development using the CCES tool chain.

Course Description:

This is a practical and interactive course that is designed to systematically teach how to use the SHARC processor to its fullest potential. Emphasis is placed on understanding the steps required to create an efficient SHARC CPU based system in the way that ADI had intended the processor to be used. Several hands on exercises provide an opportunity for the instructor to work one on one with the attendee. Throughout the workshop, attendees are encouraged to ask questions.

The CrossCore Embedded Studio (CCES) IDE is covered in detail, including topics on navigating through the IDE, projects and project configuration, the build process, and debug features. Tools based optimizations including compiler and linker optimization are covered.

An understanding of the SHARC architecture will enable getting the best performance out of the processor. Architecture topics covered include the core elements of the SHARC, which includes the Computational Units, the Data Address Generators, and the Program Sequencer. The core section is common to all members of the SHARC family. Memory configuration (both internal and external) is discussed next. Advanced instructions and SIMD operation are presented with a follow on lab on code optimization. The I/O peripherals, which include the DAI and DPI, are discussed in detail along with DMA operation between these peripherals and internal memory. A section on booting covers what happens during the boot process, creating boot image files, and discussing how to get them into the target system. Hardware development tools, such as evaluation boards and ICE's are also covered, including setting up hardware debug sessions and other hardware debug topics. An introduction into Micrium's uC/OS is also covered in the workshop.

Throughout the course, a number of hands on exercises will take the attendee through the various aspects of the software development process. Topics covered through exercises include setting up and building projects, C and Assembly language programming, various optimizations, and code debugging (simulation and hardware).

A detailed course outline can be found at WS_CCESSH5_OUT.PDF.

Who Should Attend:

System Designers needing to make informed decisions on design tradeoffs, Hardware Designers needing to develop external interfaces, and Code Developers needing to know how to get the highest performance from their algorithms. Although the focus of this workshop is on the 3rd and 4th Generation Sharc Processors, much of the workshop is applicable to other members of the SHARC family as well.

Prerequisite:

Previous embedded microprocessor experience (hardware and/or software) would be an asset.

Duration:

3.5 days

Course Fee:

Register early and save 6% on the workshop fee:
$1500 USD (North America) / €1500 EUR (Europe) - If paid by company check, wire/ACH, or money order, on or before the Run/Cancel Decision Date

$1547 USD (North America) / €1547 EUR (Europe) - If paid by credit card or PayPal, on or before the Run/Cancel Decision Date

Schedule:

This workshop can also be provided at your facilities.  Please send your request to info@kaztek.com.

Workshop participants can get 25% to 50% off the regular price on their choice of any 3 Analog Devices hardware or software development tools.
Click here to ask for more details.